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The logic synthesis workshops (LGSynth89, LGSynth91 and LGSynth93) provide behavioural models for testing, logic synthesis and optimization of circuits, see [CDDB] and [BACBL]. For more information about the models see circuits.txt.

The models are given as KISS2 files, and all are deterministic, may be partial, may include unreachable states, may omit an initial state. They specify output on transitions. We completed the KISS2 models to become deterministic, complete Mealy models in DOT format and made them available at the Mealy page. See the Kiss page for details about the KISS2 format and the completion methods used.

The circuit benchmarks have been used recently for Mealy machine testing by Hierons and Türker [HT15].